An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation

International audienceValidation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets

Timing Analysis of Binary Programs with UPPAAL

Abstract—We address the problem of computing accurate Worst-Case Execution Time (WCET). We propose a fully automatic and modular methodology based on program slicing and real-time model-checking. We have implemented our methodology and applied it to standard benchmarks. To further validate the approach, we also compare our results to the real execution times of the programs measured on a real board. I

High-level Colored Time Petri Nets for true concurrency modeling in real-time software

International audienceThe control of real-time systems often requires taking into account simultaneous access in true parallelism to shared resources. This is particularly the case for multi-core execution platforms. Timed automata or time Petri nets do not capture these features directly. We propose extending time Petri Nets with color and high-level functionality encompassing both timed multi-enableness of transitions and sequential pseudo code. We prove that the reachability problem is decidable for this model on which an on-the-fly TCTL model checking algorithm is efficiently implemented in the tool ROMÉO. We apply this approach to modeling a multi-core real time spinlock mechanism in order to check all possible execution paths and interleaving of service calls

Formal schedulability analysis based on multi-core RTOS model

International audienceVerification of real-time application schedulability is usually performed using a very abstract representation of the system which poorly supports inter-task dependencies. This paper presents the use of model-checking techniques to check the schedulability on a detailed model of a multi-core operating system. The operating system as a whole is modeled by a High-level Petri net reproducing the control flow and using the same variables as those of the implementation. Each task of the application is represented by a Stopwatch Petri Net whose transitions carry Best-Case Execution Time and Worst-Case Execution Time [BCET ,W CET ] firing intervals and make service calls to the OS. Preemption is supported by means of stopwatches. Verification is performed using observers and allows to determine the schedulability of the multi-core application, or, using parameters on the firing intervals, allows determining under which temporal conditions the application is schedulable. CCS CONCEPTS • Software and its engineering → Formal software verification; • Computer systems organization → Real-time operating systems; • Theory of computation → Verification by model checking

Control of DES with Urgency, Avoidability and Ineluctability

International audienc